Digital control system with integral clamping



DIGITAL CONTROL SYSTEM WITH INTEGRAL GLAMPING Filed Jan. 17, 1966Feb.-10-, 1970 J. o. JACQUES 13 Sheets-Sheet l A 7 mat/5 Ys Feb. l0,1970 Filed Jan. '17, 1966 J. o. JACQUES DIGITAL CONTROL SYSTEM WITHINTEGRAL CLAMPING 13 Sheefs-Sheet 2 l iwi ze' Feb. 10, 1970 Filed Jan.17, 1966 J. O. JACQUES DIGITAL CONTROL SYSTEM WITH INTEGRAL CLAMPING 1ssheets-sheet s Feb. 10, '1970 J. JAcQuEs 'DIGITAL CONTROL SYSTEMVWITHINTEGRAL CLAMPING Filed Jan. 1'7, 1966 1 3 Sheets-Smet 4 Feb.- 105 19x70J. 0.1 JACQUES 3,495,074

DIGITAL CONTROL SYSTEM WITH INTEGRAL CLAMPING Feb. 10, 1970 J.o.-J`AcQEs ,3,495,074

DGITAL CONTROL SYSTEM WITH INTEGRAL CLAMPING A al1/m27 afm/vai MMM/5L(72 cam/75@ W0@ n4 ma Mmm 044,045@ pm] a Feb. 1o, 1970 Filed Jan. 17,1966 J. O`. JACQUES DIGITAL CONTROL SYSTEM WITH INTEGRAL C'LAMPING 13Sheets-Sheet 7 DIGITALCONTROL SYSTEM WITH INTEGRAL CLAMING DIGITALCONTROL SYSTEM WITH INTEGRAL CLAMING J. o,4 JACQUES DIGITAL CONTROLSYSTEM WITHINTEGRAL CLAMPING 13 Sheets-Sheet 10 Femm, 1970 J. o.JAcQw-:s 3,495,074

D'IGITAL'CONTROL SYSTEM WITH INTEGRAL GLAMPLNG Feb. 10, 1970 Filed Jan.1 .'7, 1966 J. O. JACQUES DIGITAL CONTROL SYSTEM WITH INTEGRAL GLAMPING13 Sheets-Sheet 12 Feb.'10, 197() -.l.l o. JACQUES 3,495,074

DIGITAL CONTROL SYSTEM WITH INTEGRAL CLAMPING Filed Jan. 17. 196s 1ssheets-sheet 1s United States Patent O 3,495,074 DIGITAL CONTROL SYSTEMWITH INTEGRAL CLAMPING James O. Jacques, Boulder, Colo., assignor toInternational Business Machines Corporation, Armonk,

N.Y., a corporation of New York Filed llan. 17, 1966, Ser. No. 520,985Int. Cl. G06f 15/46 U.S. Cl. 23S-151.1 10 Claims ABSTRACT OF THEDISCLOSURE In a process controller operating a controlled device withina control range, operation of the controlled device at either limit ofthe range is caused to terminate buildup of the control signal so as toprevent unstable operati-on. 'In a two-mode control system in which anintegral quantity is generated by accumulation olf successive countsrepresentative of error values, no further counts are added, afterpredetermined limits are reached, until the controlled device is againneither fully opened or closed.

This invention relates generally to closed loop control systems, andparticularly to means for providing an integral term Iwhich does notrespond to an error signal during periods of abnormal operation.

Feedback control systems commonly compare an output or process variablesignal from a control loop with a value representing the desired outputor set point sigwhere:

P is the lcontrol signal representing the -output of the control system;

KP is the proportional gain constant;

E is the deviation or error signal;

KI is the integral gain constant;

`@Edt is the time integral of the error signal.

A more complete discussion of this type of two mode control is containedin the Handbook of Automation Computation and Control, John Wiley &Sons, vol. 3 at page 7-05.

Various implementations of this co-ntrol equation exist. The more commonform is an analog type device utilizing either pneumatic orelectricalpcomponents. There are, however, substantial dificulties inproviding versatile and accurate analog controllers for implementing theintegral term. Electrical integrators of the resistance-capacitance type`have been used to achieve reset or integration time constants of thirtyminutes. This time is in effect limited by the maximum practical sizeand cost of storage capacitors and the maximum upper limit of a stableimpedance in parallel with the storage capacitor.

ice

Circuits for providing control of integral gain in a digital'controllermust be adjustable over a wide range, while retaining substantialaccuracy as to the gain constant. At the same time, the circuits shouldbe extremely low in cost, particularly where it is necessary to useseparate gain adjustment circuits for each channel in a multichannelsystem.

It is also highly desirable, however, to provide certain features so asto improve the flexibility of the control system. Where systems using anintegral term are applied to control loops lwhich experience excursionsbeyond control limits, an unsatisfactory control action can result. Forexample, in a batch-type process the relatively long time constant ofthe integral term generally results in an unsatisfactory type control.Instabilities also result under other transient conditions, such as whena continuous process is started or stopped. These problems arise becausethe process may be unable to properly respond to control actionsignalled by the control system. For example, an actuator may be fullyopen or closed, and some time may pass before the error signal canreturn to zero with the system at a desired setpoint. The errorcomponent arising during this interval is continuously applied to theintegral term, and serves to further increase the integral term, eventhough such an increase could not further alter the actuator condition.Thus the integral term continues to wind up. and the system becomesunstable. While various pneumatic or electrical devices have beendevised in attempts to overcome this ditiiculty, they have not beenentirely successful, being either unduly expensive and complex oraffecting the normal operation of the controller.

It is therefore an object of this invention improved control system.

It is another object of this invention to provide a closed loopcontroller having a digital integrator.

A further object of this invention is to provide an improved controlsystem in which the integral action is not altered during periods inwhich the system controlled is Ibeyond control limits.

In accordance with this system, an automatic limiting action is providedyfor the integral term when the controlled device or actuator is ateither limit of its operating range.

In a specific system, an analog process variable signal isconverted intoa time interval. During the time interval, clock pulses are fed to abinary counting register causing it to count up, so as to accumulate acount repre- Senting the process variable. At the end of the timeinterval, the register contains a digital value corresponding to theanalog process variable signal. A train of pulses representing the setpoint value is then fed to the register, causing it to count in theopposite direction. The value remaining after the set point has beencounted in, is the error or difference between the process-variable andthe set point. The error signal is then converted into a pulse train andapplied to the integration gain channel for the loop. The integrationgain channel includes both a variable time switching device, termed `amulti-rate sampler, and a variable count divider. If the necessarynumber of sampling intervals have occurred, the multi-rate sampleroperates to apply the error pulse train to a series of binary triggerswhich serve to divide the pulse train by successive factors of two. Thelength of the trigger divider may be to provide an varied to establish again constant to accommodate the process loop with which it isassociated, and adjustment of the sampling interval allows a furtherrange for the integration gain constant. The carry pulses from anyselected trigger are added to the previous integral, to provide anupdated integral term. A proportional gain channel operates to provide aterm in accordance with the proportional gain constant and the errorsignal. The proportional term and the integral term are combined in theoutput register. The digital count in the output register is used tocontrol the actuator through a digital to analog converter. The outputregister includes means for establish# lishing limit conditions. Theselimit conditions are sensed, and in the event that the count is suchthat the controlled device is either fully opened or closed, themulti-rate sampler is inhibited during each scan, preventingaccumulation of additional error pulses in the integral term until suchtime as control is again achieved.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention as illustrated inthe accompanying drawings.

FIG. 1 is a generalized block diagram representation of the principalelements of a digital process system incorporating features inaccordance with the invention;

FIG. 2 is a generalized block diagram representation comprising sheetsdesignated FIGS. 2A to 2E respectively, of a digital process controllerin accordance with the invention, showing details thereof, and

FIG. 3, comprising separate sheets designated FIGS. 3A to 3G, is aseparate representation of the gating control and gate circuits utilizedin the arrangement of FIG. 2.

In the use of FIG. 2, the separate sheets designated A through Erespectively, should be aligned from left to right.

In the use of FIG. 3, the separate sheets designated A through Grespectively, should be aligned from top to bottom.

The diagram of FIG. 1 shows in generalized form a digital processcontrol system for concurrently adjusting and maintaining a number ofindividual operative set points, representing different systemvariables, within a process system 20. For the present example, it willbe assumed that twenty different variables are controlled, and that acorresponding number of controllers 21 are operated by the processcontrol system in response to directly or indirectly related valuesderived from sensors 22. The control system may be referred to thereforeas a multi-function or multiloop controller, and operates continuouslyin highly integrated fashion. The controllers 21 and sensors 22 may beconventional analog devices and need not be further described in detail.The set points are chosen or adjusted, as described in detail hereafter,in accordance with known considerations determined with respect to theprocess system 20, and may be effected by external automatic control orby operator control during operation.

Signals derived in the multiple parallel channels from the sensors 22represent the process variables (hereafter PV) and are applied to aninput multiplexer 25 that may be generalized as a first switch S1operated at a rst known rate. Signals from the input multiplexer 25 areapplied in the single output channel to an analog to digital converter26 of the type that effectively converts the amplitude of the appliedinput signal to a signal defining a variable time duration. This timeduration is used in controlling the application of clock pulses to afirst summing counter, termed the A register 28. The time intervalduring which the pulses provided from a standard clock source areapplied to the A register 28 determines, of course, the number of pulsesapplied, so that the PV value is represented in digital form.

The multi-function controller system performs a two term controlcomputation in adjusting in process variable relative to a stored setpoint. The set point is derived from a recirculating storage 30,typically a delay line system although a drum, disc or otherrecirculating memory may lbe used. Read and write circuits 31, 32respectively provide for access from and entry to the storage 30. Forease of understanding only, the read circuits 31 are shown as separatingthe set point and integral values in playback, although this separationis accomplished by conventional gating circuits. The set point (alsotermed SP herein) is entered as a digital count in the B register 35,with the A register 28 receiving the PV value. Subsequently, a series ofpulses is applied to drive the A register 28 and the B register 35 tozero, so that one value is effectively subtracted from the other. Theresult, taking into account certain limit adjustments described below,constitutes the error quantity and is presented by the A register 28 asa digital count.

The error represents the subtraction of one quantity from the other in asense dependent upon Whether forward or reverse control is used and uponthe particular limit relationships. Forward or reverse control is useddepending upon the sense in which adjustment of a given controllercauses a variation of the associated process variable. A pulse seriesand an equivalent pulse duration representative of the amplitude of theerror are provided for further processing by counting down the Aregister 28 at the clock rate.

A single term control computation would adjust the error by a givenproportional, integral, or other factor in deriving a control signalsuitable for application to the associated controller. The presentsystem provides a two term control computation in which, for eachchannel, an analog proportionality term KP and an integral term KI areeach applied to the error signal in deriving the control signal. Forthis purpose, proportional gain circuits 33 convert the pulse seriesderived from the A register 28 into a lesser number of pulses in a ratiodepending upon the proportionality factor, and apply the adjusted countto a third summing counter or C register 36 which also receives theupdated integral term in digital form from the second summing counter orB register 35. The summation of these two terms, provided as the outputsignal from the C register 36, is the output control or correctivesignal for the specific channel. The integral term is updated bycombining the summation of the previous integral term derived from theread circuits 31 with the current error level, as adjusted by theintegral gain constant in the integral gain circuits 34.

The three summing counter units 28, 35 and 36 are counted down or up,for determinable intervals, under the command of circuits heredesignated the count and count detect controls 37. The circuits 37, asdescribed in detail below, operate at chosen clock rates to drive thevarious summing counters simultaneously in the same or different sensesuntil selected states are reached. Thus, if two counters containingdifferent counts are down-counted synchronously, the count remaining inone after the other has reached zero is the difference quantity.Similarly, the count stored in one may be transferred, with or withoutmodification, into another by counting synchronously in opposite senses.

A suitably small fractional integral term may be multiplied against theincoming error signal by utilizing both a variably timed switch 38,operated in synchronism with the input and output multiplexers, and avariable pulse divider circuit 39, here designated K1'. Thus, from theintegral term for the particular channel derived from the read circuits31, and from the integral component representative of the current errorsignal derived from the integral gain circuits 34, the count applied tothe C register 36 represents the updated integral which is also replacedin storage.

The digital output signal provided from the C register 36 is appliedthrough a digital to analog converter 40, the output multiplexer 41, anda suitable holding amplifier circuit 43, so that an output controlsignal of duration suflicient to cause adjustment of the associatedcontroller is provided during the interval in which the outputmultiplexer 41 addresses the particular channel.

It will be appreciated that the system thus far broadly described has anumber of advantages as a process controller. It is extremely exible inoperation because of its organization and because of its digital nature.Set points and gain constants may be varied in operation either by theoperator or by an external data processing system, if desired, becauseindirect or direct access Vmay be had to the registers. The`manipulation of`values in digital form further permits the system to beoperated generally in conjunction with a central data processing systemwhen desired. The two term control computation improves both thestability and accuracy of this system over a single term controlcomputation. Major excursions in the error signal are correctedprincipally by the presence of the proportional term although somecontribution is also derived from the integral term. Drift and otherlong term, small magnitude, errors that would not ordinarily becorrected by the proportional term are corrected by the integral term.The integral term is digitally stored, and therefore may be retainedindefinitely without being subject to or introducing error.

This broad description of the system encompasses a substantial number ofspecific features described in detail hereafter. The drawings comprise adetailed block diagram (FIG. 2) of the system, showing the organizationof the various input and output systems as well as control and indicatordevices, including multiposition switches, individual control switches,adjustment devices and indicators. The complete system as represented inFIG. 2, comprises separate sheets denoted FIGS. 2A to 2E. While all theprincipal components are described in detail hereafter, a detaileddescription of the logical gating circuits would be repetitions forthose skilled in the art inasmuch as each of the terms applied in theform of signals to each gate is represented in the figures. It isconsidered more convenient and clear to present the various modes andgating sequences separately in FIG. 3, comprising sheets FIGS. 3A to 3G,inclusive, to provide the functioning of the logical gating circuits ina more readily visualized format.

In FIG. 3, the various principal modes of system operation areidentified as a sequence of rectangles 301-312. The individual gatesassociated with each mode are disposed in laterally extending fashion toillustrate the manner in which the specific control signals aregenerated for each control function and change of state is utilized inoperation in a particular mode. Along with the successive modes, statesor levels of the system, FIG. 3 shows the individual signals providedfrom a group of latches that are down-counted to identify the modes.Only the latches in the on condition are shown in the block identifyingthe mode. Although not shown in FIG. 2 for simplicity, the latchescontrol shift from one mode to the next in the following sequence:

`CONVERT (B01-FIG. 3A)

READY 1 (302-FIG. 3B)

`COMP-UTE ERROR (StB-FIG. 3B)

ADDRESS DELAY LINE (S04-FIG. 3C)

READY 2 (30S-FIG. 3C)

TWO TERM COMPUTE (30G-FIG. 3D)

WRITE STORAGE (307-FIG. 3E)

TRANSFER INTEGRAL TO C REG. (30S-FIG. 3E) ADVANCE CHANNEL SET DAC(E09-FIG. 3F) INTERLO-CK (310-FIG- 3G) LOAD STATE (S11-FIG. 3G)

END LOAD (312-FIG. 3G)

It will be noted that the modes are distinguished by a change of stateof the latches. At each mode, a number of gates are conditioned toprovide outputs used for further gating or advance. These gates areeither AND gates,

designated by the multiplication symbol or OR gates, designated by theaddition symbol in conventional fashion. Where gates are repeated forconvenience of reference in different parts of FIG. 3, they bear thesame numeral designation. When so shown, however, they are conditionedby different mode signals.

Shifts between the mode rectangles 301-312 in FIG. 3 are undertaken uponthe passage of gate signals through gates serially connecting therectangles and corresponding to the latch controls. Certain of theadvances are governed by signals from a Bit Ring `Circuit (generatingsignals designated BR1 through BR11 respectively) associated with therecirculating memory and described in detail below. The Bit Ring Circuitnot only governs the timing of data into and out of the recirculatingstorage, but provides a time sequence by which other gating functionsmay be performed.

It should be appreciated that for each channel separate circuits areused for set point adjustment, alarm indications and gain selection.

Referring now to FIG. 2, comprising the separate sheets designated FIGS.2A to 2E inclusive, reference is made to the separate units that aresubject to operator adjustment or control, as well as those unitspreviously broadly referred to in the description of FIG. 1. Theoperator has at his command a display function switch and a channelselect switch 52, by which a given channel may be chose for adjustmentof set point, limit or alarm conditions, for testing purposes or for theperformance of other functions. Both the display function switch 50 andthe channel select switch 52 are shown in FIG. 2D. A separate gangedarmature and contact set 52 (FIG. 2A) is provided with the channelselect switch 52 for use in a Balance operation. In FIG. 2D are also abalance switch 54 and an enter switch 55, both of the single actiontype. The latter switch 55 is more fully described as an enter set pointswitch.

At the input end of the system (FIG. 2A), the operator is able toadjust, for each channel, each of a set of four potentiometers 60, 61,62 and 63, these being the high limit, high alarm, low limit and lowalarm potentiometers respectively. Each chanenl also provides a switch67 (FIG. 2E) for selecting forward or reverse control, and in thisconjunction its should be noted that the terms Forward Positive andForward G9 Positive are the inverse of each other. At the output end ofthe system, the operator can also adjust individual potentiometers foreach channel, after engaging an automaticmanual selector switch 65appropriately to provide manual control for selection of the setting ofthe associated control unit. Additionally, there is for each channel aswitch designated as the cascade switch `68, used in the performance ofa selectable data interchange function described in greater detailbelow.

The recirculating storage 30, together with the read ampliiier and writeamplifier circuits 31, 32 respectively are shown only in general form inFIG. 2E. The addressing circuits 70 for control of entry and extractionof data from the recirculating storage 30 are also shown only generally,in asmuch as these addressing circuits may be conventional. The setpoint and integral values for each channel are stored at separatelocations in the storage, and a channel counter 72 controls sequencingof the multiplexers and other synchronously operated units bydetermining the channel at which the set point and integral values arereproduced and entered during operation. The channel counter 72 is usedin conjunction with many other gating and selection functions as well.The channel counter 72 may be a conventional step counter having oneextra position (n) in addition to the twenty positions chosen for thepresent example. It may cornprise an interconnected chain of bistableelements or a binary counter together with an output matrix, but has notbeen shown in detail for simplicity. The 21st position, designated n, isa dummy or number position 7 used for entry 'of a manually adjusted setpoint through a potentiometer 71 (FIG. 2A).

The system also employs two basic clock signals, a 1 mc. clock 73 (FIG.2B) being utilized in sequencing through various states .and in thegeneration of the serial pulse trains representative of digital counts,and a c.p.s. clock 74 (FIG. 2C) being utilized to control scanning ofthe individual channels at five times per second. These rates may beadjusted as desired, although they are representative of suitableclocking rates for data transfer and loop scanning in a typical digitalprocess control system.

The following detailed description of various operative sequencesinclpde the entry of the PV signal, the two term computation and thegeneration of the output control signal. While they may encompass allthe modes 301-312 illustrated in FIG. 3, they are not arranged inchronological order but with respect to separate functions. Concurrentlythere are described various features by which great flexibility andoperative convenience are imparted to the system Without a commensurateincrease in equipment or cost. It will be understood that thedescription is concerned primarily only with a single channel, and thatsimilar operations take place for each other channel, in sequence.

ENTRY OF DATA The following description is concerned primarily with thedeviation and conversion of the signals utilized for the subsequent twoterm control computation. Although reference is made to various parts ofFIG. 2, primary reference is to FIG. 2A, and to FIGS. 3A and 3B. Amongthe features included in this portion of the system are an arrangement[by which the analog input signal is checked for alarm violations,another feature by which the operator is prevented from utilizing a setpoint outside the present limit values, and also a feature by which newset points may be simply but readily selected and then entered into thesystem.

The analog to digital converter 26 in FIG. 2A principally uses a rampgenerator 76 that may be triggered to initiate a linearly descendingwave form under control of a circuit here shown separately as a ramp runcircuit 77. The 5 c.p.s. clock signal initiates scanning of thesuccession of channels, or the channel counter 72 shifts from onechannel to the next, starting a transitory startconvert mode (not Ishownin FIG. 3) that removes a reset bias from the ramp run circuit 77. Thisevent initiates the convert mode illustrated in FIG. 3A. With the inputmultiplexer 25 coupling an appropriate channel to the analog to digitalconverter 26, and the process variable being provided as an analogsignal on the input line, the ramp generator 76 initiates the linearlydecreasing ramp Wave form. The ramp signal is coupled to activate oneinput of each of a succession of four detection circuits labeledsuccessively the high detect circuit 80, the low detect circuit 81, thefirst detector S2 and the second detector 83. In the absence of limit oralarm conditions, the first and second detectors 82, 83 control theanalog to digital conversion. In the start-convert mode, the rampgenerator 76 continues to operate as it passes down through the level ofthe PV signal provided from the multiplexer 25. The first detector 82,however, fires whenever the ADC ramp is equal to the selected inputsignal amplitude, activating the gate 11S (FIG. 2B) and yapplying pulsesfrom the 1 mc. clock 73 to the count input of the A register 28 (FIG.2C). The counting operation and subsequent operations are describedbelow with respect to the computation function, and it suicies here tosay that the counting sequence continues until the second detector 83 isactuated at a selected reference level, here designated El.. In thepresent instance, a voltage level of one volt is selected for theminimum, or reference, and the ramp generator 76 is arranged inconventional fashion to provide a ramp signal in the range fromapproximately 6 volts downward. The set points are for convenience setin the range from 0 to 999 and are computed and displayed in this form.

Firing of the second detector 83 terminates the convert mode andinitiates a subsequent mode which may be designated as ready l (FIG.3B), in which the summing counters 28, 35, 36 are set to count inappropriate directions. A significant number of features are provided inconjunction with this basic analog to digital conversion circuitry.First it may be noted that the PV signal may be less than one volt inamplitude, so that the second detector 83 may fire before the firstdetector 82. If this occurs, during the convert mode under range gate118 (FIG, 2B and FIG. 3A) is activated, actuating an under range latch85 that reverses the sense of counting in the A register 28 (FIG. 2C)through a sequence of gates 170', 172 (also shown in FIG. 3C). Note thatin the convert mode 301 (FIG. 3A), the 2 mode control latch also is on,to fully condition the gate 170. The A register 28 is normally set tocount up when entering the PV digital value and this reversal of thesign enables an appropriate value to be entered.

A further important feature of this arrangement is the fact that itpermits the alarm settings to be determined by the potentiometers 61, 63for the particular channel. In the convert mode, a set of gates 84 (FIG.2A) coupled to the channel counter 72 (FIG. 2E) complete circuits to thehigh alarm switches 86 and low alarm switches 87 (FIG. 2A) for theparticular channel, so that these are coupled to the high and lowdetectors 80, 81 respectively. The ramp signal from the generator 76 isconcurrently applied to the high and low detectors 80, 81. A timecomparison is also made in a pair of associated gates 119, 120 (FIGS. 2Band 3A) as to the relative times in which the high, low and firstdetectors, 80-82 respectively, fire. If the first detector 82 firesprior to firing of the high detect circuit 80, the gate 120 activatesthe appropriate channel of alarm indicators 89 through input controlgates 100, 119, 120 (FIG. 2B) scanned by the channel counter 72 (FIG.2E). If the low detect circuit 81 fires prior to the first detector 82,the output of which is taken through an inverter circuit, a second ANDgate 119 coupling into the alarm indicator gating circuits is activatedfor that particular channel, as shown in FIGS. 2B and 3A. It will beappreciated that these tests and indications are provided concurrentlywith basic analog to digital conversion, so that no extra time isrequired for the alarm check. Furthermore, only relatively simple alarmcircuitry is associated with each individual channel, eliminating theneed for a central storage facility as well as the need for separatecomparison functions and equipment.

It will also be noted that high limit 90 and low limit 91 switches areprovided for each channel, these being controlled by separate channelselection gates 93 activated during the compute error mode (which mayalso be referred to as error compute) and individually selected inaccordance with the state of the channel counter 72. While the computeerror mode will be described below in conjunction with the twotermintegration, that aspect concerned with the automatic utilization ofhigh and low set point limits in the system exists during ready l and isdirectly pertinent to the input control function. To appreciate theoperation of these units, further brief discussion of the functioning ofthe B register 35 (FIG. 2D) is in order. The process variable is enteredinto the A register 28 as previously described, with the set point beingentered into the B register 35 from the storage 30' (FIG. l). This isaccomplished previous to the error compute mode, so that the tworegisters 28 and 35 may be counted down simultaneously with the numberof pulses remaining in one after the other has reached zero representingthe desired error value. Under certain conditions of operation, however,as in start-up or other transient states, the set point in the storagemay not be useful as such. Also, because of operator error or othercauses, an erroneous set point outside of limits predetermined for thesystem may be entered. The settings of the limit resistors 60, 62 areused to control the range of set points that may actually be utilized.

It should particularly be noted, however, that the low limitpotentiometer 62 is not truly a low set point element. It is moreappropriately referred to as a span limit potentiometer, because it doesnot constitute an absolute low limit but serves as a reference fromwhich an acceptable range is dened. This span limit function permitssimplification of the circuitry, and is described in detail hereafter.

In the error compute mode, the ramp generator 7,6 is again initiatedafter closure of the input switches 90, 91 controlled by the gates 93 incorrespondence to the particular channel then in use. In the errorcompute mode, the A register 26 is counted down by the clock pulses fromthe source 73 as shown by gate 150 in FIG. 3B and FIG. 2B. Initiation ofthe ramp pulse from the generator 76 causes the high detector 80 to fireiirst, coupling the l mc. clock to the A register. At the same time, 1mc. clock signals are coupled to the count input of the B register 35,through a gate 149 (FIG. 2D) that is fully activated because of thepresence of the B7-0' and the high detect signal. Thus the countdown ofboth registers 28, 35 takes place simultaneously, with the pulsesgenerated during this interval representing the set point accumulation.In this mode, the first detector 82 is not utilized, but the outputsfrom the low detector 81 and the second detector 83 (FIG. 2A) alonedetermine the total number of serial set point pulses actually used.Normally, when the set point is in the desired span, the B register willcount down to zero somewhere between the time of the firing of the lowdetector 81 and the second detector 83. If this occurs, the low detector81 iires first. Then when the BaOY signal terminates, the B75() signalinput goes false, and the output taken from the inverter goes true,representing B=. This term, plus the low detect signal activate an andgate whose output is inverted to disable the gate 150, terminating theapplication of pulses to the A register 2S.` Concurrently, the gate 149is disabled because of the termination of the B0 signal. The countremaining in the A register 28 therefore represents the error quantity.

If, however, the B register 35 counts down to zero before the lowdetector 81 or after the second detector 83, it is outside the desiredlimits. Thus, the span in which the set point must fall (given a startpoint established by the high detector 80) is actually determined at aminimum value of pulses established by the low detector 81, and themaximum value of pulses is then established by the second detector 83.This span voltage therefore defines the true set point limits.

In the event that the B register 35 counts to zero prior to the tiringof the low detector 81, counting pulses continue to be forced throughthe gate 150` for application to the A register 28 until the lowdetector 81 tires. In effect, the set point is established at its lowestlimit because the error will be largest at this point in the span. Whenthe second detector 83 tires, the gate 150 is disabled, regardless ofwhether or not the B register is at zero. This insures that thecountdown of the A register 28 is terminated upon tiring of the seconddetector 83 in any event.

To summarize, therefore, the span range is determined by the lowdetector 81, which detects the lower limit on the ramp, and also thelower limit on the set point, because if the chosen set point would givea greater error, the B register 35 counts down to zero before thedetector fires, and the detector therefore decreases the error by thisamount. On the other hand, if the stored set point is excessive, thesecond detector lires to generate the upper limit of the set point andto provide the minimum error signal. The maximum acceptable value forthe set point is set by the high limit potentiometers 60 which in effectstarts the count. The span of the set point limits, as well as theactual minimum and maximum set point values, is then determined by thesetting of the low limit potentiometer 62. For this reason, the numberof counts between the high limit and the low limit, as well as therange, are varied by adjusting only the low limit potentiometer.

Important advantages are dervied from this arrangement, inasmuch as itenables realistic set points to be used and also enables the system tobe operated under operator control during transient states. Duringstart-up for example, the set point may be set outside the limitingrange, typically at a maximum value. In this instance, the set pointthat is actually used is determined by the setting of the high limitpotentiometer which starts the set point count, because the countcontinues until the second detector 83 is tired. When the appropriatestable set point is reached as the process system moves toward a steadystate condition, the value of the setting of the high limitpotentiometer 60 can be read in the display, in a manner describedbelow, and then entered as a new set point. Another advantage of thisarrangement is that it provides an automatic fail-safe feature, in thatthe limits are continuously tested during normal operation. In the eventthat a stored set point is lost or some error occurs, the limitingvalues automatically control.

SET POINT ENTRY The manner in which the set point for an individualchannel may be varied by an operator will be principally described withrespect to FIG. 2, and principally involves the channel counter 72 (FIG.2E) the channel select switch 52 and display function switch 50 (FIG. 2Dand the set point potentiometer 71 (FIG. 2A).

It was previously stated that the channel counter 72 contains an extradigital place, constituing a dummy position designated as the number orn position. When in this 21st position, the channel counter 72 generatesa number signal to condition a gate 112 (FIG. 2A and FIG. 3A.)energizing a gate 96 that controls a 21st position switch 97 in themultiplexer 25, closing the switch to couple the set point enterpotentiometer 71 to the first detector 82. This enables a signal at alevel determined by the setting of the potentiometer 71 to be enteredinto the analog to digital converter 26. Concurrently for thisoperation, the display function switch 50 (FIG. 2D is set to the setpoint enter position, and the enter set point switch 55 is closed,actuating the enter latch 98 through a gate 203 (FIG. 2D and FIG. 3F).The system includes, as generally shown in FIG 2C, a display register99, including a resettable counter (not shown) for accumulating a seriesof pulses representative of a binary value, and appropriately convertingto decimal values for convenience. In FIGS. 2B and 3A, it is seen thatthe gate 102 is activated during the number state because of thesettings of the display function switch 50, and the channel selectswitch 52, with the display having been reset prior to this time. At thedummy or number position of the channel counter 72, therefore, the 1 mc.clock pulses are applied to the gate 102 for a duration determined bythe interval between the ring of the first detector 82 and the seconddetector 83 in the analog to digital converter 26. The pulses aretotalled in the display register 99, and the totals are displayed forthe operator. This action occurs each time the number state is reachedat the end of a scan of the various channels, or five times per second.From the standpoint of the operator, the displayed count changesconcurrently with his adjustment of the entry potentiometer 71, so thathe can directly observe in digital form the setting he is making for aparticular selected channel.

Once the chosen setting has been reached, the set point is required tobe entered into the appropriate channel and into the recirculatingstorage at the appropriate point. For this purpose, the enter latch 98is now actuated by closing of the enter set point switch 55, aspreviously described, with the channel select switch 52 being at thedesired channel position. This is accomplished during the next scan ofthe given position, by entry of the chosen set point from thepotentiometer 71 (FIG. 2A) into the B register 35 through the gate 104(FIG. 2B and FIG. 3A). The gate 104 is opened to pass 1 mc. clock pulsesfor an interval initiated by the tiring of the tirst detector 82 in theADC 26, the interval being terminated by the tiring of the seconddetector 83. The applied pulse series is accumulated in the B register35, and thereafter transferred into the recirculating storage 30 system,during succeeding modes that are discussed in detail below.

It will be noted that apart from the set point entry potentiometer 71and a relatively few gates and switches, this system utilizes existingunits of the process control system in an inter-related fashion. Theproblem of entry of a selected digital value is thereby solved atminimum expense, but with full operator convenience. These features aremade possible through the use of the dummy position in the machinecycle, and the relationship of the analog, manually controllable, inputto the analog to digital converter and the display and B registers. Adirect technique for the entry of a digital value is provided that isfar less expensive than other available expedients conventionally used.The potentiometer adjustment and cornparison to a concurrent digitaldisplay are particularly easy for an operator to utilize and understand.Furthermore, separate mechanisms are not required for each individualline, and no special addressing or other circuits are required.

It is convenient to note here that normal operation of the systemmaintains the output signal for the previous (rt-1) channel through theconvert to transfer integral to C modes (FIG. 2E), and then switches tothe newly generated signal in the advance channel mode. When usingbalance or enter for a given channel, however, the output inhibit latch398 (FIG. 2D) is set, blocking the sample and hold output signal. Thislatch is not reset on the first advance channel signal, but on the onethereafter, because the balance or enter switch 54 or 55 for the channelturns its associated latch on at the lirst advance channel signal. Thusoutput signals are not provided on the selected channel as they normallywould be.

TWO TERM COMPUTATION The function of modifying the error signal for aparticular channel in accordance with both integral and proportionalterms, selectively adjusted as to gain, has been briefly referred toabove. This portion of the system relates primarily to FIG. 2C, 2D and2E, and virtually all of FIG. 3. The following description pertains notonly to the manner in which the three summing counters 28, 35 and 36 areutilized, but particularly to the manner in which the gain adjustmentcircuits (designated 33 and 34 in FIG. 1) operate. Note that separateintegral gain circuits 34a-z inclusive are used for the differentchannels. Entry of representations into the display, and the manner ofentry into and reading from the recirculating storage, will be referredto generally here, but are set out in more detail below.

Both the A register 28 (FIG. 2C) and the B register 35 (FIG. 2D) includeten binary bits for counting from 0 to 1023. The B register 35 islimited in this respect, and does not count over-range or under-range.The A register 28, however, includes additional bits for countingoverrange and under-range. Both the registers operate as reversiblesumming counters, and have up and down inputs at which the directions ofthe counts may be reversed. Each register also includes an input towhich the pulses to be counted are applied, and a reset input, as wellas conventional means (described as part of the register for convenienceonly) for identifying predetermined counting states. In the A register28, the predetermined states are A=0 and its inverse, and A=1023 and itsinverse; in the B register 35 the predetermined states are B=0 and itsinverse, and B=1023 and its inverse. The C register 36 corresponds tothe A register 28, in that it has both under-range and over-rangeconditions, and may be counted negative prior to being counted in theopposite direction during the two term control computation.

On entering the convert mode, a gate 208 (FIG. 2D and FIG. 3F) isactuated as a function reset signal and applied to the reset input ofthe A register 28, with the B register 35 being reset through a gate 220(FIG. 2D and FIG. 3G) thereafter. Then, during the convert mode aspreviously described, the value of the process variable is entered intoand held in the A register 28. During convert also, the addressingcircuits 70 for the recirculating storage 30 (FIG. 2E) select the setpoint to be read into the B register 35 through a gate 117 (FIG. 2E andFIG. 3A). This count comprises a serial binary number read into theappropriate parallel digital positions of the B register 35 through agroup of gates 320 (FIG. 2D). Note that these gates 320 are alsoassociated with a separate data register, 319 and may, alternatively beused for the external entry of a chosen set point into the B register35. Separate gates 321 are used to read out the B register 35 contents.The C register 36 is concurrently reset through a gate 200 (FIG. 2E andFIG. 3F).

The sign of the quanity in the A register 28 is controlled by anover-range latch 322, and under-range latch and an ADC sign latch 324(FIG. 2B). The overrange latch is set by a gate 325 in the event thatthe count of A-1023 is reached prior to ring of the second detector, andlatching of this circuit 322 conditions a gate 147 during the computeerror mode to set ADC sign latch 324 positive. This in turn conditions agate 171 that controls the gate 172 (FIG. 2C and 3C) that set the Aregister 28 to count down. Various functions, insuring that properarithmetic signs are used, are employed and these are described in moredetail below. The generation of the error signal then takes place duringthe compute error mode.

Appropriate provision is further made for the nature of the controlbeing exercised, whether forward or reverse, and for the situation inwhich the process variable is under range. In the event that either theforward or positive condition obtains, the sign of the ADC sign latch324 is reversed, causing the A register 28 to count in the oppositedirection so as to effectively reverse the sense of subtraction of theprocess variable with respect to the set point. Similarly, if theunder-range latch 85 is set through the gate 118 (FIG. 2B) because thesecond detector 83 is tired before the iirst detector 82 in the ADC 26,the A register is set to count up during the compute mode because anegative quantity is in effect represented. The count down or count uprelationship at the up and down input terminals to the A register 28 isestablished by a set of gates 130, 131 and 170 responsive to theunderrange latch (FIG. 2C, FIG. 3A and lFIG. 3C).

As a result of these relationships, the system in the compute error modedrives the counts in the A register 28 and B register 35 simultaneouslyto a state in which the A register contains the error quantity. Thiserror quanity is to be passed through the gain adjustment circuits 33,34 that introduce the proportionality terms KI and KP, with the integralterm being entered into. the B register 35 (FIG. 2D) and theproportional term being entered into the C register 36 (FIG. 2E). Atthis point the A register 28 is set to count down or up, according tothe sign of the error, and the system enters an address delay line mode304 (FIG. 3C), in which the gate 117 (FIG. 2E) reads the integral fromthe recirculating storage 30 into the appropriate channel of the Bregister 35, in the manner pre- 13 viously described `with respect tothe set point. During this mode and the subsequent ready 2 mode (FIG.3C) the various sign adjustments are made (FIG. 3C).

The system therefore is enabled to enter a two term compute mode 306,shown in FIG. 3D and principally described with respect to FIG. 2C aswell. In FIG. 2C, the proportional gain circuits 33 and the integralgain circuits 34 are"`seen to receive the clock signal also applied tothe count input of the A register 28 from a gate 181 that remainsactivated until the A register 28 is brought to zero. The proportionalgain circuits 33 comprise a pair of digital count division systems, oneworking from a 1 mc. clock 340, here shown separately from the clock 73for convenience only, and the other working from a 0.7 mc. clock 342.The 1 mc. clock 340 is gated through a succession of binary countdividers 344, 345, 346 and 347, eachproviding a further half division ofthe frequency ofthe 1 mc. signal, down to a 1/16 division. The 0.7 mc.clock 342 is passed' to a succession of three binary dividers 349, 350,351, providing a succession of different values of frequency. Theamplitude of the error signal in th A register 28 is not onlyrepresented by the number of pulses contained therein, but by theduration of the count interval at 1 mc. that is used in returning the Acounter 28 to zero. Thus a group of gates 370 at the output terminals ofthe frequency dividers are controlled in part by the signal derived froman input gate 181. This signal permits a selected one of the gates 370,as controlled by the channel counter 72, a 9 position switch 371 foreach channel, to open for a time specifically related to the quantity inthe A register 28. A related number of pulses is then provided on theoutput line through separate gates 184a.-t for the channels (FIGS. 2Cand 3D) to the C register 36, for summation therein. The selection of aparticular value of frequency or count division by actuation of one ofthe gates 370 may also be controlled by the channel counter 72, througha preset gate network if desired. Alternatively, if desired, a separateproportional gain circuit 33 and integral gain circuit 34 may beutilized for each channel.

When the`A register 28 is counted down at the 1 mc. rate, theproportional gain circuits 33 operate as a variable countl divider toprovide a fractional gain constant. Through use of a cross-couplingswitch 372a-t, however, the l mc. clock pulse series may be applied tothe C register 36, while the lower pulse rate is applied to the Aregister 28, to provide a gain constant at a multiplication factor. Thusthe number of digitally related gain constants for the proportional gainterm is doubled, and the proportional term may be made predominant forchosen control loops.

In the integral gain circuits 34, the number of pulses stored in the Aregister 28 is utilized in generating the new integral term componentderived from the error signal. The integral gain circuits 34a-t, one foreach channel, include tvvo different frequency division systems, one ofwhich represents the variable frequency switch S2 designated in FIG. 1,and the other of which represents a variable frequency division system.The variable switch is designated as a multi-rate sampler 380, and maybe a preset counter operable in response to the c.p.s. clock 74, andeife'ctive to open an input gate 182 only once for each predeterminednumber of times the. channel is scanned in succession. A conventionalcounting and gating system may also be utilized for this purpose, and isof course adjustable to permit selection of this portion of the gainconstant. The remaining portion of the integral gain term is determinedby a selected count division network 383, 384, 385, here shown asconsisting of three stages for simplicity, although any additionalnumber may be used. The integral gain adjustment, therefore, is widelyvariable over a great range, depending upon the integral gain constantto be used. If a very small fractional gain quantity is to be used asthe multiplication term for the error, the multi-rate sampler 380 isclosed only once every high number of scans of that channel, opening thegate to pass the pulses representing the error term only during thatselected cycle. The number of pulses are further reduced in number inthe selectable frequency divider 383, 384, 385, so that the outputpulses passed to the B register through the gate 183 contribute only thenew component of the total updated integral term to the count of theintegral already contained in the B register 35. A rotary switch 387permits selection of the appropriate division ratio for the channel.

The two term compute mode is completed in either of two ways. When the Aregister 28 is, in the typical situation, counted down to zero, thecount terminates. Both gates 183a-t and 184a-t (FIGS. 2C and 3D) arethereafter deactivated, and the gate controlling entry into the writestorage mode 307 (FIG. 3E) is activated. Alternatively, if the Cregister 36 is saturated by reaching zero or a full count, dependentupon whether forward or reverse control is used, further pulses areblocked off from the C register at the gate 184a-t, inasmuch as thisindicates that the associated valve will be fully opened or closed.Again, the system advances to the write storage mode.

This arrangement has the advantage of providing a high division factorfor the integral term, without requiring a long string of dividers.Furthermore, both the integral and proportional gain circuits are alikein form, and operate in response to the quantity contained in the Aregister, so that no further conversion is needed. This arrangement alsoenables the proportional quantity to be given any precisely selectedincrement of gain, while the integral gain can be chosen very small.

Further significant advantages are derived from the essentially digitalnature of the integral gain circuits and the digital storage of theintegral. Where extremely low gain terms are required, analog systemshave been adopted with the consequent disadvantages of drift.

Because the integral is accumulated and stored in digital fashion, anessentially infinite time constant can be utilized, and the integralitself is effectively free from change or error. Thus the same precisionneed not be applied to each integral increment, because over a period oftime such errors will average to zero. In a practical example of asystem in accordance with the invention, the integral gain constant maybe so low that an increment is added to the integral term only once in anumber of hours or even days. Further, the selectable frequency divider383, 384, 385, provides storage of the accumulated count, so that duringthe count division none of the pulses passed by the multi-rate sampler380 are lost despite the lengthy durations of time between passage ofsamples under the control of the multi-rate sampler 380. With thisarrangement, the multi-rate sampler 380 may be a semidigital or analogdevice, such as a Staircase generator, if desired.

In the two term compute mode 306 (FIG. 3D) the B register 35 and Cregister 36 are set to count in appropriate directions by a group ofgates 174, 175, 174A and 175A (FIG. 2D). Dependent upon the source ofpulses selected in the proportional gain channel, the proportionalcomponent is passed through the gate 184 (FIG. 2C and FIG. 3D) to becounted in the C register 36, at the same time the new integralincrement is being added in an appropriate sense to the integral termstored in the B register 35.

In the next succeeding mode directly concerned with generation of thecontrol signal, the transfer integral to C mode 308 (FIG. 3E), the Cregister 36 is set to count up, the B register 35 previously having beenset to count back down to zero. The 1 mc. clock pulses are applied to agate 196 (FIG. 2D and FIG. 3E) that continues to pass the clock pulsesuntil the B register 35 returns to zero or the C register 36 is full(reaches 1023). In either event, the count remaining in the C register36 constitutes the sum of the integral and pro-

